#### 1. The number of control lines for a 8 – to – 1 multiplexer is

(A) 2

**(B)
3**

(C) 4

(D) 5

#### 2. The MSI chip 7474 is

(A) Dual edge triggered JK flip-flop (TTL).

(B) Dual edge triggered D flip-flop (CMOS).

**(C)
Dual edge triggered D flip-flop (TTL).**

(D) Dual edge triggered JK flip-flop (CMOS).

#### 3. The………. gate is also called any-or-all gate.

**(A) OR **

(B) AND

(C) NOT

(D) EX-OR

#### 4. Why is a demultiplexer called a data distributor?

(A) The input will be distributed to one of the outputs

(B) One of the inputs will be selected for the output

(C) The output will be distributed to one of the inputs

(D) Single input gives single output

#### 5. A logic gate is an electronic circuit which

**(A) Makes
logic decisions **

(B) Allows electron flow only in one direction

(C) Works on binary algebra

(D) Alternates between 0&1 values

#### 6. In positive logic, logic gate 1 corresponds to

(A) Positive voltage

**(B) Higher
voltage level **

(C) Zero voltage level

(D) Lower voltage level

#### 7. When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero.

**(A)
Sign-magnitude. **

(B) 1’s complement.

(C) 2’s complement.

(D) 9’s complement.

#### 8. A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be

**(A)
15 ns. **

(B) 30 ns.

(C) 45 ns.

(D) 60 ns.

#### 9. How many Flip-Flops are required for mod–16 counter?

(A) 5

(B) 6

(C) 3

**(D)
4**

#### 10. In negative logic, the logic state 1 corresponds to

(A) Negative logic

(B) Zero voltage

(C) More negative voltage

**(D) Lower
voltage level **

#### 11. The NAND gate output will be low if the two inputs are

(A) 00

(B) 01

(C) 10

**(D)
11**

#### 12. What is the binary equivalent of the decimal number 368

**(A)
101110000 **

(B) 110110000

(C) 111010000

(D) 111100000

#### 13. The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either

(A) A NAND or an EX-OR

(B) An OR or an EX-NOR

(C) An AND or an EX-OR

**(D)
A NOR or an EX-NOR**

#### 14. De Morgan’s first theorem shows the equivalence of

(A) OR gate and Exclusive OR gate.

**(B)
NOR gate and Bubbled AND gate.**

(C) NOR gate and NAND gate.

(D) NAND gate and NOT gate

#### 15. CMOS circuits consume power

(A) Equal to TTL

**(B)
Less than TTL**

(C) Twice of TTL

(D) Thrice of TTL