# Computer Organization and Architecture MCQ for GATE

Computer Organization and Architecture MCQ for GATE are specially prepared by our LiveMCQs team. This Computer Organisation and Architecture MCQ post cover all the possible questions for your GATE Exam. Students who are searching for Computer Organization and Architecture MCQ for GATE can read these questions for a better understanding of Computer Organization and Architecture. You can also download the PDF by clicking the link MCQ on Computer Organization and Architecture PDF provided below.

## Computer Organization and Architecture MCQ for GATE

1. The drawback of Manchester encoding is _________

(A) The cost of the encoding scheme

(B) The speed of encoding the data

(C) The Latency offered

(D) The low bit storage density provided

Answer: The low bit storage density provided

2. The read/write heads must be near to disk surfaces for better storage.

(A) True

(B) False

3.  _______ is used to detect and correct the errors that may occur during data transfers.

(A) ECC

(B) CRC

(C) Checksum

(D) None of the mentioned

4. The logic operations are simpler to implement using logic circuits.

(A) True

(B) False

5. The logic operations are implemented using _______ circuits.

(A) Bridge

(B) Logical

(C) Combinatorial

(D) Gate

6. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________

7. Which option is true regarding the carry in the ripple adders?

(A) Are generated at the beginning only

(B) Must travel through the configuration

(C) Is generated at the end of each operation

(D) None of the mentioned

Answer: Must travel through the configuration

8. In full adders the sum circuit is implemented using ________

(A) And & or gates

(B) NAND gate

(C) XOR

(D) XNOR

9. The usual implementation of the carry circuit involves _________

(A) And & or gates

(B) XOR

(C) NAND

(D) XNOR

10. A _______ gate is used to detect the occurrence of an overflow.

(A) NAND

(B) XOR

(C) XNOR

(D) AND

11. In a normal adder circuit, the delay obtained in a generation of the output is _______

(A) 2n + 2

(B) 2n

(C) n + 2

(D) None of the mentioned

12. The final addition sum of the numbers, 0110 & 0110 is ____________

(A) 1101

(B) 1111

(C) 1001

(D) 1010

13. The delay reduced to in the carry look ahead adder is __________

(A) 5

(B) 8

(C) 10

(D) 2n

14. The method followed in case of node failure, wherein the node gets disabled is _________

(A) STONITH

(B) Fibre channel

(C) Fencing

(D) None of the mentioned

15. VLIW stands for?

(A) Very Long Instruction Word

(B) Very Long Instruction Width

(C) Very Large Instruction Word

(D) Very Long Instruction Width

16. The important feature of the VLIW is _______

(A) ILP

(B) Cost effectiveness

(C) Performance

(D) None of the mentioned

17. The main difference between the VLIW and the other approaches to improve performance is ___________

(A) Cost effectiveness

(B) Increase in performance

(C) Lack of complex hardware design

(D) All of the mentioned

18. In VLIW the decision for the order of execution of the instructions depends on the program itself.

(A) True

(B) False

19. The parallel execution of operations in VLIW is done according to the schedule determined by __________

(B) Interpreter

(C) Compiler

(D) Encoder

20. The VLIW processors are much simpler as they do not require of _________

(A) Computational register

(B) Complex logic circuits

(C) SSD slots

(D) Scheduling hardware

21. The VLIW architecture follows _____ approach to achieve parallelism.

(A) MISD

(B) SISD

(C) SIMD

(D) MIMD

22. The following instruction is allowed in VLIW:

f12 = f0 * f4, f8 = f8 + f12, f0 = dm (i0, m3), f4 = pm(i8, m9);

(A) True

(B) False

23. To compute the direction of the branch the VLIW uses _____________

(A) Seekers

(B) Heuristics

(C) Direction counter

(D) Compass

24. EPIC stands for?

(A) Explicitly Parallel Instruction Computing

(B) External Peripheral Integrating Component

(C) External Parallel Instruction Computing

(D) None of the mentioned

25. For converting a virtual address into the physical address, the programs are divided into __________

(A) Pages

(B) Frames

(C) Segments

(D) Blocks

26. The memory allocated to each page is contiguous.

(A) True

(B) False

27. The pages size shouldn’t be too small, as this would lead to __________

(A) Transfer errors

(B) Increase in operation time

(C) Increase in access time

(D) Decrease in performance

28. The cache bridges the speed gap between ______ and __________

(A) RAM and ROM

(B) RAM and Secondary memory

(C) Processor and RAM

(D) None of the mentioned

29. The virtual memory bridges the size and speed gap between __________ and __________

(A) RAM and ROM

(B) RAM and Secondary memory

(C) Processor and RAM

(D) None of the mentioned

(A) MMU

(B) Translator

(C) Compiler

31. The higher order bits of the virtual address generated by the processor forms the _______

(A) Table number

(B) Frame number

(C) List number

(D) Page number

32. The page length shouldn’t be too long because ___________

(A) It reduces the program efficiency

(B) It increases the access time

(C) It leads to wastage of memory

(D) None of the mentioned

33. The lower order bits of the virtual address forms the __________

(A) Page number

(B) Frame number

(C) Block number

(D) Offset

34. The product of 1101 & 1011 is ______

(A) 10001111

(B) 10101010

(C) 11110000

(D) 11001100

35. We make use of ______ circuits to implement multiplication.

(A) Flip flops

(B) Combinatorial

(D) None of the mentioned

36. The multiplier is stored in ______

(A) PC Register

(B) Shift register

(C) Cache

(D) None of the mentioned

37. The ______ is used to coordinate the operation of the multiplier.

(A) Controller

(B) Coordinator

(C) Control sequencer

(D) None of the mentioned

38. The multiplicand and the control signals are passed through to the n-bit adder via _____

(A) MUX

(B) DEMUX

(C) Encoder

(D) Decoder

39. The product of -13 & 11 is ______________

(A) 1100110011

(B) 1101110001

(C) 1010101010

(D) 1111111000

40. The method used to reduce the maximum number of summands by half is _______

(A) Fast multiplication

(B) Bit-pair recording

(C) Quick multiplication

(D) None of the mentioned

41. The bits 1 & 1 are recorded as _______ in bit-pair recording.

(A) -1

(B) 0

(C) +1

(D) both -1 and 0

42. The multiplier -6(11010) is recorded as _______

(A) 0-1-2

(B) 0-1+1-10

(C) -2-10

(D) None of the mentioned

43.  _____ pushes the heads away from the surface as they rotate at their standard rates.

(A) Magnetic tension

(B) Electric force

(C) Air pressure

(D) None of the mentioned

44. The air pressure can be countered by putting ______ in the head-disc surface arrangement.

(A) Air filter

(B) Spring mechanism

(C) coolant

(D) None of the mentioned

45. The associatively mapped virtual memory makes use of _______

(A) TLB

(B) Page table

(C) Frame table

(D) None of the mentioned

46. The main reason for the discontinuation of semi conductor based storage devices for providing large storage space is _________

(A) Lack of sufficient resources

(B) High cost per bit value

(C) Lack of speed of operation

(D) None of the mentioned

Answer: High cost per bit value

47. The digital information is stored on the hard disk by ____________

(A) Applying a suitable electric pulse

(B) Applying a suitable magnetic field

(C) Applying a suitable nuclear field

(D) By using optic waves

Answer: Applying a suitable electric pulse

48. For the synchronization of the read head, we make use of a _______

(A) Framing bit

(B) Synchronization bit

(C) Clock

(D) Dirty bit

49. One of the most widely used schemes of encoding used is _________

(A) NRZ-polar

(B) RZ-polar

(C) Manchester

(D) Block encoding

50. The method of placing the heads and the discs in an air tight environment is also called as ______

(A) RAID Arrays

(B) ATP tech

(C) Winchester technology

(D) Fleming reduction

51. A hard disk with 20 surfaces will have _____ heads.

(A) 10

(B) 5

(C) 1

(D) 20

52. The disk system consists of which of the following?

i. Disk

ii. Disk drive

iii. Disk controller

(A) i and ii

(B) i, ii and iii

(C) ii and iii

(D) i

53. The set of corresponding tracks on all surfaces of a stack of disks form a ______

(A) Cluster

(B) Cylinder

(C) Group

(D) Set

54. The data can be accessed from the disk using _________

(A) Surface number

(B) Sector number

(C) Track number

(D) All of the mentioned

55. The read and write operations usually start at ______ of the sector.

(A) Center

(B) Middle

(C) From the last used point

(D) Boundaries

56. To distinguish between two sectors we make use of ________

(A) Inter sector gap

(B) Splitting bit

(C) Numbering bit

(D) None of the mentioned

57. The _____ process divides the disk into sectors and tracks.

(A) Creation

(B) Initiation

(C) Formatting

(D) Modification

58. The access time is composed of __________

(A) Seek time

(B) Rotational delay

(C) Latency

(D) Both Seek time and Rotational delay

Answer: Both Seek time and Rotational delay

59. The disk drive is connected to the system by using the _____

(A) PCI bus

(B) SCSI bus

(C) HDMI

(D) ISA

60. _______ is used to deal with the difference in the transfer rates between the drive and the bus.

(A) Data repeaters

(B) Enhancers

(C) Data buffers

(D) None of the mentioned

61. The sub-routine service procedure is similar to that of the interrupt service routine in ________

(A) Method of context switch

(B) Returning

(C) Process execution

(D) Method of context switch & Process execution

Answer: Method of context switch & Process execution

62. In memory-mapped I/O ____________

(A) The I/O devices and the memory share the same address space

(B) The I/O devices have a separate address space

(C) The memory and I/O devices have an associated address space

(D) A part of the memory is specifically set aside for the I/O operation

Answer: The I/O devices and the memory share the same address space

63. The usual BUS structure used to connect the I/O devices is ___________

(A) Star BUS structure

(B) Multiple BUS structure

(C) Single BUS structure

(D) Node to Node BUS structure

64. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.

(A) False

(B) True

65. The advantage of I/O mapped devices to memory mapped is ___________

(A) The former offers faster transfer of data

(B) The devices connected using I/O mapping have a bigger buffer space

(C) The devices have to deal with fewer address lines

66. The system is notified of a read or write operation by ___________

(A) Appending an extra bit of the address

(B) Enabling the read or write bits of the devices

(C) Raising an appropriate interrupt signal

(D) Sending a special signal along the BUS

Answer: Sending a special signal along the BUS

67. To overcome the lag in the operating speeds of the I/O device and the processor we use ___________

(A) BUffer spaces

(B) Status flags

(C) Interrupt signals

(D) Exceptions

68. The method of accessing the I/O devices by repeatedly checking the status flags is ___________

(A) Program-controlled I/O

(B) Memory-mapped I/O

(C) I/O mapped

(D) All of the mentioned

69. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is?

(A) Exceptions

(B) Signal handling

(C) Interrupts

(D) DMA

70. The method which offers higher speeds of I/O transfers is ___________

(A) Interrupts

(B) Memory mapping

(C) Program-controlled I/O

(D) DMA

Answer: “2012-01-10 10:40:00 EST” “2011-12-09 09:10:00 EST”

71. The process wherein the processor constantly checks the status flags is called as ___________

(A) Polling

(B) Inspection

(C) Reviewing

(D) Echoing

72. The interrupt-request line is a part of the ___________

(A) Data line

(B) Control line

(D) None of the mentioned

73. The return address from the interrupt-service routine is stored on the ___________

(A) System heap

(B) Processor register

(C) Processor stack

(D) Memory

74. The signal sent to the device from the processor to the device after receiving an interrupt is ___________

(A) Interrupt-acknowledge

(B) Return signal

(C) Service signal

(D) Permission signal

75. When the process is returned after an interrupt service ______ should be loaded again.

i) Register contents

ii) Condition codes

iii) Stack contents

(A) i, iv

(B) ii, iii and iv

(C) iii, iv

(D) i, ii

76. The time between the receiver of an interrupt and its service is ______

(A) Interrupt delay

(B) Interrupt latency

(C) Cycle time

(D) All of the mentioned

77. Interrupts form an important part of _____ systems.

(A) Batch processing

(C) Real-time processing

(D) Multi-user

78. A single Interrupt line can be used to service n different devices.

(A) True

(B) False

79. ______ type circuits are generally used for interrupt service lines.

i) open-collector

ii) open-drain

iii) XOR

iv) XNOR

(A) i, ii

(B) ii

(C) ii, iii

(D) ii, iv

80. The resistor which is attached to the service line is called _____

(A) Push-down resistor

(B) Pull-up resistor

(C) Break down resistor

(D) Line resistor

81. The data is stored on the disk in the form of blocks called _____

(A) Pages

(B) Frames

(C) Sectors

(D) Tables

82. The transfer rate, when the USB is operating in low-speed of operation is _____

(A) 5 Mb/s

(B) 12 Mb/s

(C) 2.5 Mb/s

(D) 1.5 Mb/s

83. The high speed mode of operation of the USB was introduced by _____

(A) ISA

(B) USB 3.0

(C) USB 2.0

(D) ANSI

84. The sampling process in speaker output is a ________ process.

(A) Asynchronous

(B) Synchronous

(C) Isochronous

(D) None of the mentioned

85. The USB device follows _______ structure.

(A) List

(B) Huffman

(C) Hash

(D) Tree

86. The I/O devices form the _____ of the tree structure.

(A) Leaves

(B) Subordinate roots

(C) Left subtrees

(D) Right subtrees

87. USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers.

(A) True

(B) False

88. In USB the devices can communicate with each other.

(A) True

(B) False

(C) Logging

(D) Debugging

89. The device can send a message to the host by taking part in _____ for the communication path.

(A) Arbitration

(B) Polling

(C) Prioritizing

(D) None of the mentioned

90. When the USB is connected to a system, its root hub is connected to the ________

(A) PCI BUS

(B) SCSI BUS

(C) Processor BUS

(D) IDE

91. The devices connected to USB is assigned a ____ address.

(A) 9 bit

(B) 16 bit

(C) 4 bit

(D) 7 bit

92. The USB address space can be shared by the user’s memory space.

(A) True

(B) False

93. The initial address of a device just connected to the HUB is ________

(A) AHFG890

(B) 0000000

(C) FFFFFFF

(D) 0101010

94. Locations in the device to or from which data transfers can take place is called ________

(A) End points

(B) Hosts

(C) Source

(D) None of the mentioned

95. A USB pipe is a ______ channel.

(A) Simplex

(B) Half-Duplex

(C) Full-Duplex

(D) Both Simplex and Full-Duplex

96. The type/s of packets sent by the USB is/are _______

(A) Data

(C) Control

(D) Both Data and Control

97. The first field of any packet is _____

(A) PID

(C) ENDP

(D) CRC16

98. The 4 bit PID’s are transmitted twice.

(A) True

(B) False

99. The last field in the packet is ______

(A) PID

(C) ENDP

(D) CRC

100. The CRC bits are computed based on the values of the _____

(A) PID