# TOP 100+ Logic Gate MCQs and Answers with FREE PDF

The Logic Gate MCQs and Answers section of our website is a simulation of the real exam for its visitors. When you’re taking the Logic Gate Training for your company, you should always know the answers to the MCQs. Knowing the answers will not only help you pass your test but also give you an edge over your co-workers. Of course, you should spend a lot of time reviewing and studying the material, but it won’t do you any good if you can’t answer some Theory questions on the test. I’m here to help with that. Here are some Logic Gate MCQs and Answers that will help you pass your test.

## Logic Gate MCQs and Answers

1. Which of the following gates is described by the expression?

A. OR

B. AND

C. NOR

D. NAND

2. What is the Boolean expression for a four-input OR gate?

A. Y = A + B + C + D

B. Y = A· B · C · D

C. Y = A – B – C – D

D. Y = A \$ B \$ C \$ D

3. How many truth table entries are necessary for a four-input circuit?

A. 4

B. 8

C. 12

D. 16

4. What does the small bubble on the output of the NAND gate logic symbol mean?

A. open collector output

B. tristate

C. The output is inverted.

D. none of the above

5. What are the pin numbers of the outputs of the gates in a 7432 IC?

A. 3, 6, 10, and 13

B. 1, 4, 10, and 13

C. 3, 6, 8, and 11

D. 1, 4, 8, and 11

6. The output of a NOT gate is HIGH when ________.

A. the input is LOW

B. the input is HIGH

C. power is applied to the gate’s IC

D. power is removed from the gate’s IC

7. How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go HIGH?

A. any one of the inputs

B. any two of the inputs

C. any three of the inputs

D. all four inputs

8. If the output of a three-input AND gate must be a logic LOW, what must the condition of the inputs be?

A. All inputs must be LOW.

B. All inputs must be HIGH.

C. At least one input must be LOW.

D. At least one input must be HIGH.

9. Logically, the output of a NOR gate would have the same Boolean expression as a(n):

A. NAND gate immediately followed by an inverter

B. OR gate immediately followed by an inverter

C. AND gate immediately followed by an inverter

D. NOR gate immediately followed by an inverter

10. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?

A. The dim indication on the logic probe indicates that the supply voltage is probably low.

B. The output of the gate appears to be open.

C. The dim indication is the result of a bad ground connection on the logic probe.

D. The gate is a tristate device.

11. What is the Boolean expression for a three-input AND gate?

A. X = A + B + C

B. X = A · B · C

C. A – B – C

D. A \$ B \$ C

12. How many entries would a truth table for a four-input NAND gate have?

A. 2

B. 8

C. 16

D. 32

13. The Boolean expression for a 3-input OR gate is ________.

A. X = A + B

B. X = A + B + C

C. X = ABC

D. X = A + BC

14. From the truth table for a three-input NOR gate, what is the only condition of inputs A, B, and C that will make the output X high?

A. A = 1, B = 1, C = 1

B. A = 1, B = 0, C = 0

C. A = 0, B = 0, C = 1

D. A = 0, B = 0, C = 0

15. The logic gate that will have a LOW output when any one of its inputs is HIGH is the:

A. NAND gate

B. AND gate

C. NOR gate

D. OR gate

16. The output of a NAND gate is LOW if ________.

A. all inputs are LOW

B. all inputs are HIGH

C. any input is LOW

D. any input is HIGH

17. Which of the following gates has the exact inverse output of the OR gate for all possible input combinations?

A. NOR

B. NOT

C. NAND

D. AND

18. What is the difference between a 7400 and a 7411 IC

A. 7400 has two four-input NAND gates; 7411 has three three-input AND gates

B. 7400 has four two-input NAND gates; 7411 has three three-input AND gates

C. 7400 has two four-input AND gates; 7411 has three three-input NAND gates

D. 7400 has four two-input AND gates; 7411 has three three-input NAND gates

19. The output of an exclusive-OR gate is HIGH if ________.

A. all inputs are LOW

B. all inputs are HIGH

C. the inputs are unequal

D. none of the above

20. A clock signal with a period of 1 s is applied to the input of an enable gate. The output must contain six pulses. How long must the enable pulse be active?

A. Enable must be active for 0 s.

B. Enable must be active for 3 s.

C. Enable must be active for 6 s.

D. Enable must be active for 12 s.